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SLG505YC64L
Clock Synthesizer for Intel PCI-Express Chipset
Features
* * * * * * * SLG505YC64 is fully compliant to Intel CK505 clock specification Ideal for both desktop and mobile application TME (Trusted Mode Enable) input to disable over-clocking support New "SR" type differential output to reduce power consumption and improve signal integrity
Output Summary
* * * * * * * * 2- differential CPU clock outputs @ 0.7V 1 - selectable differential CPU/SRC clock output @ 0.7V 1 - selectable differential DOT96/SRC clock output @ 0.7V 9 - differential Serial Reference Clock (SRC) clock outputs @ 0.7V 1 - differential SATA clock output @ 0.7V 1 - single-ended 48MHz clock output @ 3.3V 6 - single-ended 33MHz clock outputs @ 3.3V 1 - single-ended 14.318MHz clock output @ 3.3V
CLK_REQ# inputs to support SRC clock power managewww..com ment 3.3 and low voltage (0.8V) I/O Power Supply 64 pin TSSOP Package
Table 1. Frequency Select Table (FS_C, FS_B, FS_A)
F S _ C 0 0 0 0 1 1 1 1 F S _ B 0 0 1 1 0 0 1 1 F S _ A 0 1 0 1 0 1 0 1 DOT_ 96 (MHz) 96.0 96.0 96.0 96.0 96.0 96.0 96.0
Pin Configuration
PCI_0/CLKREQ_A# USB (MHz) 48.0 48.0 48.0 48.0 48.0 48.0 48.0 VDD_PCI PCI_1/CLKREQ_B# TME/PCI_2 PCI_3 PCI_4/SRC_5_EN PCIF_5/ITP_EN VSS_PCI VDD_48 USB/FS_A VSS_48 VDD_I/O SRC_0/DOT_96 SRC_0#/DOT_96# VSS_I/O VDD_PLL3 SRC_1/PROG_SE_1 SRC_1#/PROG_SE_2 VSS_PLL3 VDD_PLL3_I/O SRC_2/SATA SRC_2#/SATA# VSS_SRC SRC_3/CLKREQ_C# SRC_3#/CLKREQ_D# VDD_SRC_I/O SRC_4 SRC_4# VSS_SRC SRC_9 SRC_9# SRC_11#/CLKREQ_G# 1 2 3 4 5 6 7 81 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SCL SDA REF/FS_C/TEST_SEL VDD_REF XTAL_IN XTAL_OUT VSS_REF FS_B/TEST_MODE CKPWRGD/PD# VDD_CPU CPU_0 CPU_0# VSS_CPU CPU_1_AMT CPU_1_AMT# VDD_CPU_I/O I/O_Vout SRC_8/CPU_ITP SRC_8#/CPU_ITP# VDD_SRC_I/O SRC_7/CLKREQ_F# SRC_7#/CLKREQ_E# VSS_SRC SRC_6 SRC_6# VDD_SRC PCI_STOP#/SRC_5 CPU_STOP#/SRC_5# VDD_SRC_I/O SRC_10# SRC_10 SRC_11/CLKREQ_H#
CPU (MHz) 266.6 133.3 200.0 166.6 333.3 100.0 400.0
SRC (MHz) 100.0 100.0 100.0 100.0 100.0 100.0 100.0
PCI (MHz) 33.3 33.3 33.3 33.3 33.3 33.3 33.3
REF (MHz) 14.318 14.318 14.318 14.318 14.318 14.318 14.318
Reserved
Table 2. PROG_SE_1 and PROG_SE_2 Configuration
B 1 b 4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 1 b 3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B 1 b 2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B 1 b 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 24.576MHz 24.576MHz 98.304MHz 27MHz 25MHz Reserved Reserved Reserved PROG_SE_1 Pin 17 SRC_1 SRC_1 (LCD_CLK Stdby) LCD_CLK (-0.5% SS) LCD_CLK (-1.0% SS) LCD_CLK (-1.5% SS) LCD_CLK (-2.0% SS) LCD_CLK (-2.5% SS) PROG_SE_2 Pin 18 SRC_1# SRC_1# (LCD_CLK Stdby) LCD_CLK# (-0.5% SS) LCD_CLK# (-1.0% SS) LCD_CLK# (-1.5% SS) LCD_CLK# (-2.0% SS) LCD_CLK# (-2.5% SS) 24.576MHz 98.304MHz 98.304MHz 27MHz 25MHz
SLG505YC64L
Reserved
64-pin TSSOP
Other brands and names may be claimed as the property of others
Silego Technology, Inc. 000-0084505L-10
Rev 1.0 Revised February 15, 2007
SLG505YC64L
Pin Description
Pin # 1 2 3 4
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Name PCI_0/CLKREQ_A# VDD_PCI PCI_1/CLKREQ_B# TME/PCI_2
Type I/O, SE PWR I/O, SE I/O, SE 3.3V power supply for outputs.
Description Configurable PCI clock output or CLKREQ input. Configurable PCI clock output or CLKREQ input. PCI clock output. TME (Trusted Mode Enabled) strap input. Only SLG84505 supports TME input. In SLG84515, this pin will be defined as PCI_2 output. PCI clock output. PCI clock output. When SRC_5_EN is sampled HIGH during CKPWRGD assertion, it will configure PCI_STOP#/SRC_5 and CPU_STOP#/SRC_5# as SRC_5 and SRC_5# respectively. When SRC_5_EN is sampled LOW, it will configure these pins as PCI_STOP# and CPU_STOP#. Free running PCI clock output. When ITP_EN input is sampled HIGH during CKPWRGD assertion, it will configure CPU_ITP/SRC_8 as CPU output. Ground for outputs. 3.3V power supply for outputs. USB clock output. Frequency Select input to determine CPU output frequency. Ground for outputs. Low voltage I/O power supply for outputs. Configurable SRC or 96 MHz DOT clock output. Configurable SRC or 96 MHz DOT clock output. Ground for outputs. 3.3V power supply for outputs. Configurable SRC or Programmable SE output. SE output can be configured as 24.576MHz, 27MHz or 25MHz. Configurable SRC or Programmable SE output. SE output can be configured as 24.576MHz, 27MHz or 25MHz. Ground for outputs. Low voltage I/O power supply for outputs. Configurable Serial Reference clock for SATA or PCI Express device. Configurable Serial Reference clock for SATA or PCI Express device. Ground for outputs. Configurable differential CPU clock output or CLKREQ input. Configurable differential CPU clock output or CLKREQ input. Low voltage I/O power supply for outputs. Differential Serial Reference Clock output. Differential Serial Reference Clock output. Page 2 of 27
5 6
PCI_3 PCI_4/SRC_5_EN
O, SE I/O, SE
7
PCIF_5/ITP_EN
I/O, SE
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
VSS_PCI VDD_48 USB/FS_A VSS_48 VDD_I/O SRC_0/DOT_96 SRC_0#/DOT_96# VSS_I/O VDD_PLL3 SRC_1/PROG_SE_ 1 SRC_1#/PROG_SE _2 VSS_PLL3 VDD_PLL3_I/O SRC_2/SATA SRC_2#/SATA# VSS_SRC SRC_3/CLKREQ_C # SRC_3#/CLKREQ_ D# VDD_SRC_I/O SRC_4 SRC_4#
GND PWR I/O, SE GND PWR O, DIF O, DIF GND PWR O, DIF/SE O, DIF/SE GND PWR O, DIF O, DIF GND I/O I/O PWR O, DIF O, DIF
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SLG505YC64L
Pin Description (continued)
Pin # 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 SRC_9 SRC_9# SRC_11#/CLKREQ_ G# SRC_11/CLKREQ_H SRC_10 SRC_10# VDD_SRC_I/O CPU_STOP#/SRC_ 5# PCI_STOP#/SRC_5 VDD_SRC SRC_6# SRC_6 VSS_SRC SRC_7#/CLKREQ_ E# SRC_7/CLKREQ_F# VDD_SRC_I/O SRC_8#/CPU_ITP# Name VSS_SRC Type GND O, DIF O, DIF I/O I/O O, DIF O, DIF PWR I/O I/O PWR O, DIF O, DIF GND I/O I/O PWR O, DIF Ground for outputs. Differential Serial Reference Clock output. Differential Serial Reference Clock output. Configurable differential CPU clock output or CLKREQ input. Configurable differential CPU clock output or CLKREQ input. Differential Serial Reference Clock output. Differential Serial Reference Clock output. Low voltage I/O power supply for outputs. Configurable CPU_STOP# input or differential Serial Reference Clock output. Configurable PCI_STOP# input or differential Serial Reference Clock output. 3.3V power supply for outputs. Differential Serial Reference Clock output. Differential Serial Reference Clock output. Ground for outputs. Configurable differential CPU clock output or CLKREQ input. Configurable differential CPU clock output or CLKREQ input. Low voltage I/O power supply for outputs. Selectable differential CPU or SRC output. It will configure as CPU clock when ITP_EN is sampled HIGH. It will configure as SRC clock when ITP_EN is sampled LOW. Selectable differential CPU or SRC output. It will configure as CPU clock when ITP_EN is sampled HIGH. It will configure as SRC clock when ITP_EN is sampled LOW. I/O voltage reference output. Low voltage I/O power supply for outputs. Differential CPU Clock output. Differential CPU Clock output. Ground for outputs. Differential CPU Clock output. Differential CPU Clock output. 3.3V power supply for outputs. CKPWRGD is a 3.3V LVTTL iput. It acts as a level sensitive strobe to latch the FS pins and other multiplexed inputs. After CKPWRGD assertion, it becomes a real time input for asserting power down (active high). Frequency Select input to determine CPU output frequency. When in test mode, FS_B/TEST_MODE will configure outputs to run at REF or Hi-Z. 0 = Hi-Z, 1 = REF Description
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47
SRC_8/CPU_ITP
O, DIF
48 49 50 51 52 53 54 55 56
I/O_Vout VDD_CPU_I/O CPU_1_AMT# CPU_1_AMT VSS_CPU CPU_0# CPU_0 VDD_CPU CKPWRGD/PD#
O, SE PWR O, DIF O, DIF GND O, DIF O, DIF PWR I
57
FS_B/TEST_MODE
I
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SLG505YC64L
Pin Description (continued)
Pin # 58 59 60 61 62
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Name VSS_REF XTAL_OUT XTAL_IN VDD_REF REF/FS_C/TEST_S EL
Type GND O, SE I PWR I/O, SE Ground for outputs. 14.318MHz crystal output. 14.318MHz crystal input. 3.3V power supply for outputs.
Description
14.318 reference clock output. When FS_C/TEST_SEL input is pulled to 3.3V during CKPWRGD# assertion, the device will configure into TEST MODE. Refer to DC Parameters section for FS input voltage threshold. After CKPWRGD assertion, this pin will be configured as REF output. Serial Interface bus data input and output. Serial Interface bus clock input.
63 64
SDA SCL
I/O, SE I
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SLG505YC64L
Block Diagram
XTAL_IN XTAL XTAL_OUT CPU_0, CPU_1_AMT PLL1 CPU_ITP, SRC_8 SRC_1, 3:7, SRC_9:11 REF
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SCL, SDA PD# CPU_STOP# PCI_STOP# CKPWRGD PLL3 FS_A:C ITP_EN TME TEST_MODE, TEST_SEL CLKREQ_A:H# PLL2 Serial Interface & Control Logic PLL4
PCI_0:4, PCIF_5
PROG_SE_0:1 / PROG_DIFF
SATA / SRC_2
DOT_96 / SRC_0
USB
Figure 1. Simplified Block Diagram
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SLG505YC64L
Selecting N-Divider and M-Divider Value to Change CPU output Frequency
1. Select M-divider Value a. The M-Divider value for the desired CPU output frequency is determined by the current CPU frequency mode and Spread Spectrum mode. The following N-Divider Value Table lists the recommended M-divider value associated with each CPU frequncy mode and Spread Spectrum option. 2. Select N-divider Value a. The N-divider value is calcuated based on the following equation. N-divider value = ((Target Frequency - Base Frequency) / Frequency Resolution) + N-Divider Base Value
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b. The N-Divider Base Value and Frequency Resolution for the desired CPU output frequency is determined by the current CPU Frequency mode and Spread Spectrum mode, and they are listed under the following N-Divider Value Table. c. For example, the N-divider value for 170MHz under the "100MHz Frequency and Spread Spectrum OFF Mode" will be "755". 755 = ((170 - 100) / 0.2237) + 442
N-Divider and M-Divider Value for Different CPU Output Frequency
Table 3. N-Divider Value Table CPU Frequency Mode 100MHz 133MHz 166MHz 200MHz 266MHz 333MHz 400MHz 100MHz 133MHz 166MHz 200MHz 266MHz 333MHz 400MHz Spread Spectrum Mode OFF or Center OFF or Center OFF or Center OFF or Center OFF or Center OFF or Center OFF or Center Down Down Down Down Down Down Down CPU Frequency Range 100 to 180 133 to 240 166 to 240 200 to 360 266 to 480 333 to 480 400 to 720 100 to 180 133 to 240 166 to 240 200 to 360 266 to 480 333 to 480 400 to 720 Recommended M-Divider Value 14 14 10 14 14 10 14 13 13 10 13 13 10 13 N-Divider Base Value 442 442 414 442 442 414 442 413 413 413 413 413 413 413 Maximum N-Divider Value 799 799 598 799 799 598 799 748 748 597 748 748 597 748 Frequency Resolution 0.2237 0.2983 0.3977 0.4474 0.5966 0.7955 0.8949 0.2386 0.3182 0.3977 0.4773 0.6364 0.7955 0.9546
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SLG505YC64L
Selecting N-Divider and M-Divider Value to Change SRC output Frequency
1. Select M-divider Value a. The M-Divider value for the desired SRC output frequency is determined by the current CPU frequency mode and Spread Spectrum mode. The following N-Divider Value Table lists the recommended M-divider value associated with each CPU frequncy mode and Spread Spectrum option. 2. Select N-divider Value a. The N-divider value is calcuated based on the following equation. N-divider value = ((Target Frequency - Base Frequency) / Frequency Resolution) + N-Divider Base Value
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b. The N-Divider Base Value and Frequency Resolution for the desired SRC output frequency is determined by the current CPU Frequency mode and Spread Spectrum mode, and they are listed under the following N-Divider Value Table. c. For example, the N-divider value for 105MHz under the "100MHz Frequency and Spread Spectrum OFF Mode" will be "435". 435 = ((105 - 100) / 0.2386) + 414
N-Divider and M-Divider Value for Different SRC Output Frequency
Table 4. N-Divider Value Table CPU Frequency Mode 166MHz, 333MHz 166MHz, 333MHz 100MHz, 133MHz, 200MHz, 266MHz, 400MHz 100MHz, 133MHz, 200MHz, 266MHz, 400MHz Spread Spectrum Mode OFF or Center Down OFF or Center Down CPU Frequency Range 100 to 120 100 to 120 100 to 120 100 to 120 Recommended M-Divider Value 10 10 14 13 N-Divider Base Value 414 413 442 413 Maximum N-Divider Value 498 497 531 497 Frequency Resolution 0.2386 0.2386 0.2237 0.2386
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SLG505YC64L
Low Voltage type "SR" differential output buffer
The CK505 utilizes a new output buffer for all differential clocks. The low power type SR buffer is a departure from the type X buffer used in previous CK410 clock generators. The type SR buffer uses efficient NMOS push-pull drivers powered off a low voltage power rail, offering a reduction in power consumption, improve edge rate performance, and cross point voltage control.
3.3V 0.8V Nominal
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T-Line Z = 50 ohm
Receiver
Rs
PLL Core
Rs
T-Line Z = 50 ohm
Figure 2. Type SR Differential Output Buffer
CK505 Integrated Linear Regulator and Control
The CK505 features an internal regulator to provide a low voltage reference not possible with common discrete low dropout (LDO) linear regulators. An on-die comparator is used to drive the variable IO_Vout reference voltage to an external pass element such as a common 2N3904 (SOT23) NPN transistor for platform using a Vin > +1.5V or a BSS138 MOSFET for platforms using a Vin < +1.5V to provide a low voltage power supply for the type SR buffers.
VDD_I/O = 0.8V Nominal Vin = 1.5V to 3.3V
CK505
3.3V R1 = 33
R2 = 15
_
Vref
I/O_Vout
Q1 = 2N3904 C1 = 100pF VDD_I/O = 0.8V Nominal C_Bulk = 40uF (min)
+
Figure 3. CK505 Integrated Linear Regulator
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SLG505YC64L
Output Drive Status Summary
Table 5. Output drive status for PCI_STOP#, CPU_STOP#, CR# asserted and SMBus OE disabled PCI_STOP# asserted Single-ended clocks Differential Clocks Stoppable Non-Stoppable Stoppable Non-Stoppable CPU_STOP# asserted CR# asserted SMBus OE Disabled
Driven low Running Clock driven high Clock# driven low Running
Running Running Clock driven high Clock# driven low Running
Running Running Clock driven low Clock# driven low Running
Driven low Clock driven low or 20K pulldown Clock# driven low
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Table 6. Output drive status during different power management state All Single-ended Clocks w/o strap Latches Open State Powerdown M1 *Virtual Power Cycle to latches Open w strap All Differential Clocks, Except CPU1 Clock Clock# Clock CPU1 Clock#
Low Low Low
Hi-Z Hi-Z Hi-Z
Low or 20K pulldown Low or 20K pulldown Low or 20K pulldown
Low Low Low
Low or 20K pulldown Low or 20K pulldown Running
Low Low Running
Clock output status indentical to "Latches Open State"
*Note: Virtual Power Cycle - Latches open is accomplished by first programming the PD_RESTORE bit, byte 0, bit 0 = 0 which clears all configuration registers upon assertion of PD# low. Upon detection of PD# low, it will immediately go to "Latches Open State" and all registers and state machines will be reset as if a full power cycle has oocurred.
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SLG505YC64L
Serial Bus Interface
A two-wire serial interface is provided as the programming interface for the clock synthesizer. The serial interface is fully compliance to the SMBus 2.0 specification. The registers associated with the two-wire interface initializes to their default setting upon power-up, and therefore use of this interface is optional. The serial interface supports block write and block read operation from any SMBus master devices. For block write and block read operations, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. The block write and block read protocol is outlined in Table 7. The slave receiver address is 11010010 (D2h).
Table 7. Block Read and Block Write protocol
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Block Write Protocol Description Bit
Block Read Protocol Description
Bit
1 2:8 9 10 11:18 19 20:27 28 29:36 37 38:45 46 .... .... .... ....
Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 Bit '00000000' stands for block operation Acknowledge from slave Byte Count - 8 bits Acknowledge from slave Data byte 0 - 8 bits Acknowledge from slave Data byte 1 - 8 bits Acknowledge from slave Data Byte N/Slave Acknowledge... Data Byte N - 8 bits Acknowledge from slave Stop
1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39:46 47 48:55 56 .... .... .... ....
Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 Bit '00000000' stands for block operation Acknowledge from slave Repeat start Slave address - 7 bits Read Acknowledge from slave Byte count from slave - 8 bits Acknowledge Data byte from slave - 8 bits Acknowledge Data byte from slave - 8 bits Acknowledge Data bytes from slave/Acknowledge Data byte N from slave - 8 bits Not Acknowledge Stop
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SLG505YC64L
Table 8. Byte Read and Byte Write protocol Byte Write Protocol Bit Description Bit Byte Read Protocol Description
1 2:8 9 10
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Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits '1xxxxxxx' stands for byte operation bit[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Data byte - 8 bits Acknowledge from slave Stop
1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39
Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits '1xxxxxxx' stands for byte operation bit[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Repeat start Slave address - 7 bits Read Acknowledge from slave Data byte from slave - 8 bits Not Acknowledge Stop
11:18 19 20:27 28 29
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SLG505YC64L
Control Register Summary
Control Register 0 Bit Type Description/Function Power up condition
7 6 5 4
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R R R RW
Reflected the value of FS_C pin sampled on power up Reflected the value of FS_B pin sampled on power up Reflected the value of FS_A pin sampled on power up iAMT Enable 0 = Legacy Mode 1 = iAMT Mode Note: Once this bit is set, it cannot be disabled or cleared by writing a "0". This bit can only be cleared by a power-on-reset. Reserved Reserved Note: In CK505 clock specification, this bit is defined as SRC output PLL source and it is based on a 3-PLL architecture. We do not implement this bit because SLG505YC64L uses a 4-PLL architecure and generate SRC clock from a dedicate PLL. We use a 4_PLL architecture to optimize SRC clock jitter performance.
X X X 0
3 2
RW RW
0 0
1
RW
SATA output PLL source 0 = Same source as SRC outputs 1 = PLL2 (48M PLL) and fixed at 100MHz Configuration control for power down mode 0 = Upon assertion of PD#, the clock generator will initiate a full reset. Under this condition, the clock generator will emulate a cold power on reset internally and re-latch the FS input pins 1 = Legacy PD# input mode
0
0
RW
1
Control Register 1 Bit Type Description/Function Power up condition
7
RW
SRC_0 and DOT_96 output selection 0 = SRC_0 output 1 = DOT_96 output PLL1 (CPU PLL) center spread enable 0 = down spread 1 = center spread PLL3 (PCIEX PLL) center spread enable 0 = down spread 1 = center spread Note: This bit has no impact if SRC clocks are sourced from PLL1 (CPU PLL)
0
6
RW
0
5
RW
0
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SLG505YC64L
Control Register 1 (continued) Bit Type Description/Function Power up condition
4:1
RW
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PLL3 (PCIEX PLL) configuration control 0000 = PLL3 disabled, SRC_1 uses the same PLL as other SRC outputs 0001 = 100MHz 0.5% (SSC standby, PLL3 on, SRC_1 uses the same PLL as other SRC outputs) 0010 = 100MHz 0.5% (only SRC_1 sourced from PLL3) 0011 = 100MHz 1.0% (only SRC_1 sourced from PLL3) 0100 = 100MHz 1.5% (only SRC_1 sourced from PLL3) 0101 = 100MHz 2.0% (only SRC_1 sourced from PLL3) 0110 = 100MHz 2.5% (only SRC_1 sourced from PLL3) 0111 = Reserved 1000 = 24.576MHz for Prog_SE_1 & Prog_SE_2 (1394A support) 1001 = 24.576MHz for Prog_SE_1 & 98.304Mhz for Prog_SE_2 (1394A/B support) 1010 = 98.304MHz for Prog_SE_1 & Prog_SE_2 (1394B support) 1011 = 27MHz for Prog_SE_1 & Prog_SE_2 1100 = 25MHz for Prog_SE_1 & Prog_SE_2 1101 = Reserved 1110 = Reserved 1111 = Reserved PCI outputs PLL source 0 = PLL1 (CPU PLL) 1 = same source as SRC outputs
0001
0
RW
1
Control Register 2 Bit Type Description/Function Power up condition
7
RW
REF Output Enabled 0 = Disabled 1 = Enabled 48MHz Output Enabled 0 = Disabled 1 = Enabled PCIF_5 Output Enabled 0 = Disabled 1 = Enabled PCI_4 Output Enabled 0 = Disabled 1 = Enabled PCI_3 Output Enabled 0 = Disabled 1 = Enabled PCI_2 Output Enabled 0 = Disabled 1 = Enabled PCI_1 Output Enabled 0 = Disabled 1 = Enabled PCI_0 Output Enabled 0 = Disabled 1 = Enabled
1
6
RW
1
5
RW
1
4
RW
1
3
RW
1
2
RW
1
1
RW
1
0
RW
1
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SLG505YC64L
Control Register 3 Bit Type Description/Function Power up condition
7
RW
SRC_11 Output Enabled 0 = Disabled 1 = Enabled SRC_10 Output Enabled 0 = Disabled 1 = Enabled SRC_9 Output Enabled 0 = Disabled 1 = Enabled SRC_8/CPU_ITP Output Enabled 0 = Disabled 1 = Enabled SRC_7 Output Enabled 0 = Disabled 1 = Enabled SRC_6 Output Enabled 0 = Disabled 1 = Enabled SRC_5 Output Enabled 0 = Disabled 1 = Enabled SRC_4 Output Enabled 0 = Disabled 1 = Enabled
1
6
RW
1
5 www..com 4
RW
1
RW
1
3
RW
1
2
RW
1
1
RW
1
0
RW
1
Control Register 4 Bit Type Description/Function Power up condition
7
RW
SRC_3 Output Enabled 0 = Disabled 1 = Enabled SATA/SRC_2 Output Enabled 0 = Disabled 1 = Enabled SRC_1 Output Enabled 0 = Disabled 1 = Enabled SRC_0/DOT_96 Output Enabled 0 = Disabled 1 = Enabled CPU_1 Output Enabled 0 = Disabled 1 = Enabled CPU_0 Output Enabled 0 = Disabled 1 = Enabled PLL1 (CPU PLL) Spread Spectrum enable 0 = Disabled 1 = Enabled
1
6
RW
1
5
RW
1
4
RW
1
3
RW
1
2
RW
1
1
RW
1
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SLG505YC64L
Control Register 4 (continued) Bit Type Description/Function Power up condition
0
RW
PLL3 (PCIEX PLL) Spread Spectrum enable 0 = Disabled 1 = Enabled Note: This bit has no impact if SRC clocks are sourced from PLL1 (CPU PLL)
1
Control Register 5
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Type
Description/Function
Power up condition
7
RW
CLKREQ_A# enable 0 = Configure pin 1 as PCI_0 output 1 = Configure pin 1 as CLKREQ_A# input CLKREQ_A# mapping 0 = SRC_0 1 = SRC_2 CLKREQ_B# enable 0 = Configure pin 3 as PCI_1 output 1 = Configure pin 3 as CLKREQ_B# input CLKREQ_B# mapping 0 = SRC_1 1 = SRC_4 CLKREQ_C# enable 0 = Configure pin 24 as SRC_3 output 1 = Configure pin 24 as CLKREQ_C# input Note: To configure this pin as CLKREQ_C# input, SRC_3 needs to be disabled by clearing Byte[4], bit[7] to "0" before setting this bit.
0
6
RW
0
5
RW
0
4
RW
0
3
RW
0
2
RW
CLKREQ_C# mapping 0 = SRC_0 1 = SRC_2 CLKREQ_D# enable 0 = Configure pin 25 as SRC_3# output 1 = Configure pin 25 as CLKREQ_D# input Note: To configure this pin as CLKREQ_D# input, SRC_3 needs to be disabled by clearing Byte[4], bit[7] to "0" before setting this bit.
0
1
RW
0
0
RW
CLKREQ_D# mapping 0 = SRC_1 1 = SRC_4
0
Control Register 6 Bit Type Description/Function Power up condition
7
RW
CLKREQ_E# enable 0 = Configure pin 43 as SRC_7# output 1 = Configure pin 43 as CLKREQ_E# input to control SRC_6 output Note: To configure this pin as CLKREQ_E# input, SRC_7 needs to be disabled by clearing Byte[3], bit[3] to "0" before setting this bit.
0
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Control Register 6 (continued) Bit Type Description/Function Power up condition
6
RW
CLKREQ_F# enable 0 = Configure pin 44 as SRC_7 output 1 = Configure pin 44 as CLKREQ_F# input to control SRC_8 output Note: To configure this pin as CLKREQ_F# input, SRC_7 needs to be disabled by clearing Byte[3], bit[3] to "0" before setting this bit.
0
5
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RW
CLKREQ_G# enable 0 = Configure pin 32 as SRC_11# output 1 = Configure pin 32 as CLKREQ_G# input to control SRC_9 output Note: To configure this pin as CLKREQ_G# input, SRC_11 needs to be disabled by clearing Byte[3], bit[7] to "0" before setting this bit.
0
4
RW
CLKREQ_H# enable 0 = Configure pin 33 as SRC_11 output 1 = Configure pin 33 as CLKREQ_H# input to control SRC_10 output Note: To configure this pin as CLKREQ_H# input, SRC_11 needs to be disabled by clearing Byte[3], bit[7] to "0" before setting this bit.
0
3 2 1
RW RW RW
Reserved Reserved PCI_STOP# control for SSCD output 0 = Free-running 1 = SSCD clock are stopped when PCI_STOP# is active PCI_STOP# control for SRC outputs 0 = Free-running 1 = SRC clock are stopped when PCI_STOP# is active
0 0 0
0
R
0
Control Register 7 Bit Type Description/Function Power up condition
7 6 5 4 3 2 1 0
R R R R R R R R
Revision ID bit 3 Revision ID bit 2 Revision ID bit 1 Revision ID bit 0 Vendor ID bit 3 Vendor ID bit 2 Vendor ID bit 1 Vendor ID bit 0
0 0 0 0 0 1 1 0
Control Register 8 Bit Type Description/Function Power up condition
7:4
R
Device ID 0000 = 56 pin TSSOP or SSOP 0001 = 64 pin TSSOP 0010 to 1111 = Reserved Reserved Reserved
0001
3 2
RW RW
0 0
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SLG505YC64L
Control Register 8 (continued) Bit Type Description/Function Power up condition
1
RW
Prog_SE_1 output enable 0 = Disabled 1 = Enabled Prog_SE_2 output enable 0 = Disabled 1 = Enabled
0
0
RW
0
www..com Register 9 Control
Bit
Type
Description/Function
Power up condition
7
RW
PCI_STOP# control for PCIF_5 0 = Free-running 1 = PCIF_5 is stopped when PCI_STOP# is active Trusted mode enabled input status 0 = Normal operation (full function) 1 = Trusted mode enabled (no over-clocking allowed) REF output drive strength control 0 = 1x (2 loads) 1 = 2x (3 loads) REF or Tristate Select for Test Mode 0 = Tristate 1 = REF Test Clock Mode Entry Control 0 = Normal operation 1 = REF or Tristate mode IO_VOUT control 000 = 0.3V 001 = 0.4V 010 = 0.5V 011 = 0.6V 100 = 0.7V 101 = 0.8V 110 = 0.9V 111 = 1.0V
0
6
R
X
5
RW
1
4
RW
0
3
RW
0
2:0
RW
101
Control Register 10 Bit Type Description/Function Power up condition
7
R
SRC_5_EN input strap status 0 = Pins are configured as CPU_STOP# and PCI_STOP# inputs 1 = Pins are configured as SRC_5 and SRC_5# outputs. Reserved Reserved Reserved Allow control of CPU_1_AMT with assertion of CPU_STOP# 0 = Free Running 1 = Stopped with CPU_STOP# asserted Allow control of CPU_0 with assertion of CPU_STOP# 0 = Free Running 1 = Stopped with CPU_STOP# asserted
X
6 5 4:2 1
RW RW RW RW
0 0 000 1
0
RW
1
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SLG505YC64L
Control Register 11 Bit Type Description/Function Power up condition
7:0
RW
Reserved
00000000
Control Register 12 Bit Type Description/Function Power up condition
7:6 www..com 5:0
RW RW
Reserved Byte count register for block read operation Note: The default value is 13. To read more than 13 bytes, system BIOS needs to change this register to the number of bytes it intends to read.
00 001101
Control Register 13 Bit Type Description/Function Power up condition
7 6 5:0
RW RW RW
Vendor Manufacturing/Production Test Mode. Please write with "0" Vendor Manufacturing/Production Test Mode. Please write with "0" Reserved
0 0 000000
Control Register 14 (Frequency Table Control) Bit Type Description/Function Power up condition
7
RW
Frequency Select Source 0 = HW (Latched FS inputs) 1 = SW (Output frequency controlled by the value of bit[6:2] Note: This bit will be forced to a "0" when TME is enabled.
0
6:2
RW
SW Frequency Select bit[4:0] Note: Default settings for bit[2:0] are determined by the latched value of FS_C to FS_A inputs.
00xxx
1 0
RW RW
Reserved Reserved
0 1
Control Register 15 (Programmable CPU PLL M-Divider Value) Bit Type Description/Function Power up condition
7:6 5:0
RW RW
CPU PLL N-Divider Value bit[1:0] CPU PLL M-Divider Value bit[5:0]
00 000000
Control Register 16 (Programmable CPU PLL N-Divider Value) Bit Type Description/Function Power up condition
7:0
RW
CPU PLL N-Divider Value bit[9:2]
00000000
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SLG505YC64L
Control Register 17 (Programmable CPU/SRC Control) Bit Type Description/Function Power up condition
7
RW
CPU PLL M/N Control 0 = Disabled 1 = Enabled Note: This bit will be forced to a "0" when TME is enabled.
0
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6
RW
SRC PLL M/N Control 0 = Disabled 1 = Enabled Note: This bit will be forced to a "0" when TME is enabled.
0
5 4:0
RW RW
Reserved Reserved
0 00000
Control Register 18 (Watchdog Timer Value) Bit Type Description/Function Power up condition
7
RW
Time Base Select 0 = 293.6 msec 1 = 1.174 second Reserved Hard Alarm Watchdog Timer Value 000 = 0 x Time base (0 sec.) 001 = 4 x Time base (1.176 or 4.704 sec.) 010 = 8 x Time base (2.352 or 9.408 sec.) 011 = 12 x Time base (3.528 or 14.112 sec.) 100 = 16 x Time base (4.704 or 18.816 sec.) 101 = 20 x Time base (5.880 or 23.520 sec.) 110 = 24 x Time base (7.056 or 28.224 sec.) 111 = 28 x Time base (8.232 or 32.928 sec.) Reserved
0
6:5 4:2
RW RW
00 001
1:0
RW
10
Control Register 19 (Watchdog Timer Control) Bit Type Description/Function Power up condition
7
RW
Watchdog Enable 0 = Stop Watchdog Timer 1 = Enable Watchdog. Timer will start counting down after a frequency change occurs Watchdog Hard Alarm Time-out Status 0 = No time-out occurs (read). Ignore (write) 1 = Hard Alarm time-out occurred (read). Clear Watchdog Hard Alarm time-out status bit (write) Reserved Reserved Reserved Reserved Reserved
0
6
RW
0
5 4 3 2 1
RW RW RW RW RW
0 0 0 0 0
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SLG505YC64L
Control Register 19 (Watchdog Timer Control) (continued) Bit Type Description/Function Power up condition
0
RW
Reserved
0
Control Register 20 (Drive strength Control) Bit Type Description/Function Power up condition
7
www..com
RW
48MHz clock drive strength control 0 = Normal 1 = High Reserved Reserved PCIF_5 output drive strength 0 = Normal 1 = High Reserved PCI_3:4 output drive strength 0 = Normal 1 = High Reserved PCI_0:2 output drive strength 0 = Normal 1 = High
0
6 5 4
RW RW RW
1 1 0
3 2
RW RW
1 0
1 0
RW RW
1 0
Control Register 21 (Manufacturing Test Control) Bit Type Description/Function Power up condition
7:1 0
RW RW
Reserved Manufacturing Test Control. Write with "0".
000000 0
Control Register 22 (Programmable SRC PLL M-Divider Value) Bit Type Description/Function Power up condition
7:6 5:0
RW RW
SRC PLL N-Divider Value bit[1:0] SRC PLL M-Divider Value bit[5:0]
00 000000
Control Register 23 (Programmable SRC PLL N-Divider Value) Bit Type Description/Function Power up condition
7:0
RW
SRC PLL N-Divider Value bit[9:2]
00000000
Control Register 24 to 28 (Reserved) Bit Type Description/Function Power up condition
7:0
RW
Reserved
X
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SLG505YC64L
Crystal Recommendations
The SLG505YC64L requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the SLG505YC64L to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300ppm frequency shift between series and parallel crystals due to incorrect loading.
Table 9. Crystal Recommendations. Frequency (Fund) Cut Loading Load Cap Drive (max.) Shunt Cap (max.) Motional (max.) Cut Accuracy (max.) Temp Stability (max.) Aging (max.)
14.31818MHz
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AT
Parallel
20pF
0.1mW
5pF
0.016pF
35ppm
30ppm
5ppm
Absolute Maximum Ratings
Max VDD Supply Voltage (VDD_3.3):.............................4.6V Max VDD_I/O Supply Voltage (VDD_I/O): ......................1.5V Max Input Voltage (Vih):..................................................4.6V Min Input Voltage (Vil):...................................................-0.5V Storage Temperature::............................... -65C to + 150C Operating Temperature (Ambient, no airflow): . 0C to +70C ESD Protection (Min):.................................................. 2000V
DC Electrical Characteristics
Operating Conditions
Symbol VDD_3.3 Vih Vil Vih_FS_Test Description 3.3V Supply Voltage Input High Voltage (SE) Input Low Voltage (SE) Input High Voltage (SE) Conditions 5% Min 3.135 2.0 VSS-0.3 2.0 0.7 VSS-0.3 Typ Max 3.465 VDD+0.3 0.8 VDD+0.3 1.5 0.35 +5 Unit V V V V V V uA V 0.4 0.72 1.5 0.88 5 6 7 250 25 80 1.0 0.1 25 8.0 V V pF pF nH mA mA mA mA mA mA
Vih_FS_Normal Input High Voltage (FS) Vil_FS_Normal Input Low Voltage (FS) Iil Voh Vol VDD_I/O Cin Cout Lpin Idd_3.3V Idd_IO_0.8V Idd_PD_3.3V Idd_PD_0.8V Idd_M1_3.3V Idd_M1_0.8V Input Leakage Current Output High Voltage (SE) Output Low Voltage (SE) Low Voltage Differential I/O Supply Voltage Input Pin Capacitance Output Pin Capacitance Pin Inductance Operating Supply Current, default configuration Differential I/O current, all output enabled Powerdown Supply Current, 3.3V Powerdown Supply Current, 0.8V M1 Mode Supply Current, 3.3V M1 Mode Supply Current, 0.8V
0 < Vin < VDD Ioh = -1mA Iol = 1mA
-5 2.4
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SLG505YC64L
AC Electrical Characteristics
Differential Outputs (CPU, SRC, DOT_96) Timing Characteristics
Symbol Laccurracy Tperiod Tperiod Tperiod www..com Tperiod Tperiod Tperiod Tperiod Tperiod Tperiod Tperiod Tperiod Tperiod Tperiod Tperiod Tperiod Tperiod Tperiod Tabs Tabs Tabs Tabs Tabs Tabs Tabs Tabs Tabs Tabs Tabs Tabs Tabs Tabs Tabs Tabs Tabs Description Long term accuracy Average CPU Period (100MHz, SSC disabled) Average CPU Period (133MHz, SSC disabled) Average CPU Period (166MHz, SSC disabled) Average CPU Period (200MHz, SSC disabled) Average CPU Period (266MHz, SSC disabled) Average CPU Period (333MHz, SSC disabled) Average CPU Period (400MHz, SSC disabled) Average CPU Period (100MHz, SSC enabled) Average CPU Period (133MHz, SSC enabled) Average CPU Period (166MHz, SSC enabled) Average CPU Period (200MHz, SSC enabled) Average CPU Period (266MHz, SSC enabled) Average CPU Period (333MHz, SSC enabled) Average CPU Period (400MHz, SSC enabled) Average SRC Period (100MHz, SSC disabled) Average SRC Period (100MHz, SSC enabled) Average DOT_96 Period (96MHz) Absolute Min/Max CPU Period (100, SSC disabled) Absolute Min/Max CPU Period (133, SSC disabled) Absolute Min/Max CPU Period (166, SSC disabled) Absolute Min/Max CPU Period (200, SSC disabled) Absolute Min/Max CPU Period (266, SSC disabled) Absolute Min/Max CPU Period (333, SSC disabled) Absolute Min/Max CPU Period (400, SSC disabled) Absolute Min/Max CPU Period (100, SSC enabled) Absolute Min/Max CPU Period (133, SSC enabled) Absolute Min/Max CPU Period (166, SSC enabled) Absolute Min/Max CPU Period (200, SSC enabled) Absolute Min/Max CPU Period (266, SSC enabled) Absolute Min/Max CPU Period (333, SSC enabled) Absolute Min/Max CPU Period (400, SSC enabled) Absolute Min/Max SRC Period (100, SSC disabled) Absolute Min/Max SRC Period (100, SSC enabled) Absolute Min/Max DOT_96 Period (96MHz) 9.997001 7.497751 5.998201 4.998500 3.748875 2.999100 2.499250 9.997001 7.497751 5.998201 4.998500 3.748875 2.999100 2.499250 9.997001 9.997001 10.41354 9.912001 7.412751 5.913201 4.913500 3.663875 2.914100 2.414250 9.912001 7.412751 5.913201 4.913500 3.663875 2.914100 2.414250 9.872001 9.872001 10.16354 Min. Max. 300 10.003000 7.502251 6.001801 5.001500 3.751125 3.000900 2.500750 10.05327 7.539950 6.031960 5.026634 3.769975 3.015980 2.513317 10.003000 10.05327 10.41979 10.08800 7.587251 6.086801 5.086500 3.836125 3.085900 2.585750 10.13827 7.624950 6.116960 5.111634 3.854975 3.100980 2.598317 10.12800 10.17827 10.66979 Unit ppm ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Conditions
Using frequency counter with the measurement interval equal or greater than 0.15 second Average period over 1 us Average period over 1 us Average period over 1 us Average period over 1 us Average period over 1 us Average period over 1 us Average period over 1 us Average period over 1 us Average period over 1 us Average period over 1 us Average period over 1 us Average period over 1 us Average period over 1 us Average period over 1 us Average period over 1 us Average period over 1 us Average period over 1 us
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SLG505YC64L
Differential Outputs (CPU, SRC, DOT_96) Timing Characteristics
Symbol Slew_rise Rising slew rate Description Min. 2.5 Max. 8.0 Unit V/ns Conditions
1. Use `average' acquisition mode of the scope 2. Measurement taken from differential waveform 3. Slew rate measured through V_swing voltage range centered about differential zero 1. Use `average' acquisition mode of the scope 2. Measurement taken from differential waveform 3. Slew rate measured through V_swing voltage range centered about differential zero 1. Use `average' acquisition mode of the scope 2. Measurement taken from single ended waveform 3. Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculation Measurement taken from differential waveform 1. Measurement taken from single ended waveform 2. V_cross is defined as the voltage where Clock = Clock# 3. Only applies to the differential rising edge (i.e. Clock rising and Clock# falling) 1. Measurement taken from single ended waveform 2. V_cross is defined as the voltage where Clock = Clock# 3. V_cross delta is defined as the total variation of all crossing voltages of rising Clock and falling Clock#
Slew_fall
Falling slew rate
2.5
8.0
V/ns
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Slew_var
Slew rate matching
20
%
V_swing
Differential output swing
300
mV
V_cr
Crossing point voltage
300
550
mV
V_cr_dlt
Variation of V_cr
140
mV
Tccjitter Tccjitter Tccjitter Duty Cycle Tskew Tskew Tskew
Cycle to Cycle Jitter (CPU) Cycle to Cycle Jitter (SRC) Cycle to Cycle Jitter (DOT_96) Duty Cycle Pin-to-Pin Skew (CPU_0 & CPU_1) Pin-to-Pin Skew (CPU_2) Pin-to-Pin Skew (all SRC outputs) 45
85 125 250 55 100 150 TBD
ps ps ps % ps ps ps
PCI Timing Characteristics
Symbol Laccurracy Tperiod Tperiod Tabs Tabs Thigh Tlow Description Long term accuracy Average Period (SSC disabled) Average Period (SSC enabled, -0.5%) Absolute Min/Max Period (SSC disabled) Absolute Min/Max Period (SSC enabled, -0.5%) CLK high time CLK low time 29.99100 29.99100 29.49100 29.49100 12 12 Min Max 300 30.00900 30.15980 30.50900 30.65980 N/A N/A Units ppm ns ns ns ns ns ns Conditions
1. Measured with respect to 1.5V 2. Using frequency counter with the measurement interval equal or greater than 0.15s, target frequency is 33.333333MHz 1. Measured with respect to 1.5V 2. Average period over any 1us period of time 1. Measured with respect to 1.5V 2. Average period over any 1us period of time
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SLG505YC64L
PCI Timing Characteristics
Symbol Edge Rate Rising edge rate Description Min 1.0 Max 4.0 Units V/ns Conditions Measured from 0.4V to 2.4V in test board, measured from 0.8V to 2.0V in system Measured from 0.4V to 2.4V in test board, measured from 0.8V to 2.0V in system Measured with respect to 1.5V Measured with respect to 1.5V
Edge Rate
Falling edge rate
1.0
4.0
V/ns
Tccjitter Duty Cycle
Cycle to cycle jitter Duty Cycle Pin-to-Pin Skew 45
500 55 1000
ps % ps
www..com Tskew
USB_48 Timing Characteristics
Symbol Laccurracy Tperiod Tabs Thigh Tlow Edge Rate Description Long term accuracy Average Period Absolute Min/Max Period CLK high time CLK low time Rising edge rate 20.83125 20.48125 8.094 7.694 1.0 Min Max 300 20.83542 21.18542 10.036 9.836 2.0 Units ppm ns ns ns ns V/ns Measured from 0.4V to 2.4V in test board, measured from 0.8V to 2.0V in system Measured from 0.4V to 2.4V in test board, measured from 0.8V to 2.0V in system Measured with respect to 1.5V Measured with respect to 1.5V Conditions
1. Measured with respect to 1.5V 2. Using frequency counter with the measurement interval equal or greater than 0.15s, target frequency is 48.000000MHz 1. Measured with respect to 1.5V 2. Average period over any 1us period of time
Edge Rate
Falling edge rate
1.0
2.0
V/ns
Tccjitter Duty Cycle
Cycle to cycle jitter Duty Cycle 45
350 55
ps %
REF Timing Characteristics
Symbol Laccurracy Tperiod Tabs Thigh Tlow Edge Rate Description Long term accuracy Average Period Absolute Min/Max Period CLK high time CLK low time Rising edge rate 69.82033 68.82033 TBD TBD 1.0 Min Max 300 69.86224 70.86224 TBD TBD 4.0 Units ppm ns ns ns ns V/ns Measured from 0.4V to 2.4V in test board, measured from 0.8V to 2.0V in system Measured from 0.4V to 2.4V in test board, measured from 0.8V to 2.0V in system Measured with respect to 1.5V Measured with respect to 1.5V Conditions
1. Measured with respect to 1.5V 2. Using frequency counter with the measurement interval equal or greater than 0.15s, target frequency is 14.318180MHz 1. Measured with respect to 1.5V 2. Average period over any 1us period of time
Edge Rate
Falling edge rate
1.0
4.0
V/ns
Tccjitter Duty Cycle
Cycle to cycle jitter Duty Cycle 45
1000 55
ps %
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SLG505YC64L
Measurement Points for Differential Clocks
Single ended (SE) measurement waveforms
Vmax = 1.15V Clock# Vcross max = 550mV Vcross min = 300mV Clock Vmin = - 0.30V Clock# Vmin = - 0.30V Vcross max = 550mV Vcross min = 300mV Vmax = 1.15V
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Vcross delta = 140mV
Vcross delta = 140mV
Clock
Clock#
Clock# Vcross median + 75mV
Tr is e
Vcross median
Vcross median Vcross median 75mV
ll Tf a
Clock
Clock
Differential (DIFF) measurement waveforms
Clock Period (Differential) Positive Duty Cycle (Differential) Negative Duty Cycle (Differential)
0.0V Clock - Clock#
0.0V
Rise Edge Rate
Fall Edge Rate
Vih = +150mV 0.0V Vil = +150mV Clock - Clock#
Vih = +150mV 0.0V Vil = +150mV
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SLG505YC64L
Ordering Information
SLG xxx YC y z TR
Tape & Reel (optional) Package Type Revision Code Intel Yellow Cover Compliant Device Device Part number (CK505) Company Prefix
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Part Number
Package Type
Temperature Range
SLG505YC64LT SLG505YC64LTTR
64 Lead Green Package TSSOP 64 Lead Green Package TSSOP - Tape and Reel
Commercial, 0 to 70C Commercial, 0 to 70C
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SLG505YC64L
Package Drawing and Dimensions
64 Lead TSSOP Package
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